1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor device having a multi-layered pad and a manufacturing method thereof that reduces cracks by optimizing the structure of a bonding pad.
2. Discussion of Related Art
Beginning with the development of deep sub-micron technology, a combination of W-plug, Al-flow, and Chemical Mechanical Polishing (CMP) processes is required in the manufacture of multi-layered wiring for semiconductor devices.
The W-plug process, used to produce multi-layered wiring, is needed to generate uniform contact holes or via contact holes during the CMP process in manufacturing semiconductor devices. The CMP process requires the use of a new bonding pad instead of conventional bonding pad having a wide via contact hole because many residual particles such as etching byproducts or slurry exist in the boundary of pad regions. This is particularly true when tungsten (W) is used in the CMP process with the conventional bonding pad. These residual particles adversely affect the adhesion of gold balls during wire bonding. Consequently, the gold balls exfoliate from the surface of the pad and increase the electrical resistance of the bonding pad.
FIG. 1 is a cross-sectional view of a semiconductor device having a conventional multi-layered pad formed using the W-plug process. In the figure, only the structure of the region of interest is shown. The semiconductor device having the multi-layered pad structure shown is fabricated in three steps.
In the fist step, a first interlevel insulating layer 22 is formed and planarized in the pad forming region on a semiconductor substrate. The semiconductor substrate includes a field oxide layer (not shown), transistors (not shown), and capacitors (not shown). A first conductive pad 24 consisting of an Al or a Cu alloy is formed in the pad forming region on the first interlevel insulating layer 22. A second interlevel insulating layer 28 consisting of an oxide material is formed on the first conductive pad 24. The second interlevel insulating layer 28 is then selectively etched to form a first plurality of via holes 26, exposing a defined part of the first conductive pad 24 for electrical connection to a second conductive pad that will be formed later. To facilitate the subsequent step of depositing a conductive layer consisting of tungsten (W), a barrier metal layer (not shown) having a Ti/TiN laminated structure is formed only in the via holes 26. The tungsten (W) conductive layer is formed on the second interlevel insulating layer 28 using a Chemical Vapor Deposition (CVD) method and planarized using the CMP method. By doing so a first tungsten (W) plug 27 is formed in the first plurality of via holes 26.
In the second step, a second conductive pad 30 consisting of an Al or a Cu alloy is formed on a defined region of the second interlevel insulating layer 28 for electrical connection to the first tungsten (W) plug 27. Analogously to the first step, a third interlevel insulating layer 34 having a second plurality of via holes 32 is formed on the second interlevel insulating layer 28. In this manner, a second tungsten (W) plug 33 is formed in the second plurality of via holes 32.
In the third step, a third conductive pad 36 consisting of an Al or a Cu alloy is formed on a defined region of the third interlevel insulating layer 34 for electrical connection to the second tungsten (W) plug 33. Then, a protective layer 38 is disposed on a defined region of the third conductive pad 36 and the third interlevel insulating layer 34, exposing the third conductive pad 36 that forms a pad window region 40. The pad window region 40 is used to wire bond Au balls or Au bumps.
FIG. 2 is a top plan view of the multi-layered pad for the semiconductor device shown in FIG. 1. Referring to FIG. 2, the first to third conductive pads 24, 30, and 36, respectively, underlying the pad window region 40 are electrically connected with one another through the tungsten (W) plugs 27 and 33 formed in the first and second plurality of via holes 26 and 32, respectively, of the first and second interlevel insulating layers 28 and 34, respectively. Thus, the conductive pads and the leads (not shown) are wire-bonded via the pad window region 40 defined on the third conductive pad 36.
FIG. 1 is a cross-sectional view taken along the line I--I of FIG. 2, wherein reference numeral 10a denotes the pad forming region and reference numeral 10b indicates the connection between a cell and the pad forming region 10a.
When using the multi-layered pad as shown in the cross-sectional view of FIG. 1, it may be somewhat possible to prevent the exfoliation of gold balls from the surface of pads and the consequent increase of electrical resistance of the bonding pad. However, the conductive pads are placed under mechanical stress by the probing that occurs during device testing. The mechanical stress often causes cracks 42 to appear in the interlevel insulating layers. Such cracks may also appear during wire bonding where the overlying conductive pad 18 and leads (not shown) are electrically connected in the pad window.
Since the soft conductive pad--consisting of an Al alloy--is interposed between the hard interlevel insulating layers, the stress applied in the direction indicated by the arrow shown in FIG. 1 causes a distortion of the conductive pad that creates cracks 42 in the pad and interlevel insulating layers. This phenomenon is similar to breaking glass positioned between two cushions. The cracks 42 produced in the interlevel insulating layers may create wire bonding defects or the deterioration of assembly characteristic of the semiconductor package.